Physical Design Methodology Engineer
We are looking for a Physical Design Methodology Engineer.
As part of our DPU silicon team, you will help lead the way for our cutting-edge ASICs, supporting world-class silicon Physical Design.
Required/Minimum
Qualifications:
7
years of related technical engineering experienceo OR Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 4
years technical engineering experience or internship experienceo OR Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 3
years technical engineering experience or internship experienceo OR Doctorate degree in Electrical Engineering, Computer Engineering, Computer Science, or related field.
7
years of physical design experience, including hands-on experience in synthesis, place & route, and STA.
4
years of experience with Synopsys design tools (DC, ICC2/Fusion-Compiler, PrimeTime).
2
years of experience on scripting (TCL/Perl) and/or flow automationOther requirements:
Ability to meet Microsoft, customer and/or government security screening requirements are required for this role.
These requirements include but are not limited to the following specialized security screenings:
Microsoft Cloud Background Check:
This position will be required to pass the Microsoft Cloud Background Check upon hire/transfer and every two years thereafter.
Preferred
Qualifications:
10
years of physical design experience (including synthesis, place & route, LEC, STA, physical verification, and EM/IR).
Experience developing/maintaining a production flow environment supporting synthesis, PnR, LEC, STA, etc.
Deep understanding of timing constraints, including derates & margins, CDC issues, clock constraints, budgeting, etc.
Demonstrated tapeout experience in TSMC 7nm or below, or comparable.
Silicon Engineering IC4 - The typical base pay range for this role across the U.
S.
is USD $112,000 - $218,400 per year.
There is a different range applicable to specific work locations, within the San Francisco Bay area and New York City metropolitan area, and the base pay range for this role in those locations is USD $145,800 - $238,600 per year.
Certain roles may be eligible for benefits and other compensation.
Find additional benefits and pay information here:
https:
//careers.
microsoft.
com/us/en/us-corporate-payMicrosoft will accept applications for the role until May 16, 2024.
Microsoft is an equal opportunity employer.
All qualified applicants will receive consideration for employment without regard to age, ancestry, color, family or medical care leave, gender identity or expression, genetic information, marital status, medical condition, national origin, physical or mental disability, political affiliation, protected veteran status, race, religion, sex (including pregnancy), sexual orientation, or any other characteristic protected by applicable laws, regulations and ordinances.
We also consider qualified applicants regardless of criminal histories, consistent with legal requirements.
If you need assistance and/or a reasonable accommodation due to a disability during the application or the recruiting process, please send a request via the Accommodation request form.
Benefits/perks listed below may vary depending on the nature of your employment with Microsoft and the country where you work.
#azurehwjobs #HIFEOwnership of flows and automation for critical tools (place & route, extraction/STA, physical verification, etc); deploy and test new flows; debug issues & improve existing flows.
Work closely with Physical Design and Front End team members across functions and geographies to monitor, track, and resolve issues in tools and design flows.
Work with tool vendors to resolve key design challenges, improve our flows, and resolve tool issues.
Work closely with Physical Design team members to drive quality and QOR improvements.
Employment typeFull-TimeWork siteUp to 50% work from homeRole typeIndividual ContributorDisciplineSilicon EngineeringProfessionHardware Engineering.
Estimated Salary: $20 to $28 per hour based on qualifications.
As part of our DPU silicon team, you will help lead the way for our cutting-edge ASICs, supporting world-class silicon Physical Design.
Required/Minimum
Qualifications:
7
years of related technical engineering experienceo OR Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 4
years technical engineering experience or internship experienceo OR Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 3
years technical engineering experience or internship experienceo OR Doctorate degree in Electrical Engineering, Computer Engineering, Computer Science, or related field.
7
years of physical design experience, including hands-on experience in synthesis, place & route, and STA.
4
years of experience with Synopsys design tools (DC, ICC2/Fusion-Compiler, PrimeTime).
2
years of experience on scripting (TCL/Perl) and/or flow automationOther requirements:
Ability to meet Microsoft, customer and/or government security screening requirements are required for this role.
These requirements include but are not limited to the following specialized security screenings:
Microsoft Cloud Background Check:
This position will be required to pass the Microsoft Cloud Background Check upon hire/transfer and every two years thereafter.
Preferred
Qualifications:
10
years of physical design experience (including synthesis, place & route, LEC, STA, physical verification, and EM/IR).
Experience developing/maintaining a production flow environment supporting synthesis, PnR, LEC, STA, etc.
Deep understanding of timing constraints, including derates & margins, CDC issues, clock constraints, budgeting, etc.
Demonstrated tapeout experience in TSMC 7nm or below, or comparable.
Silicon Engineering IC4 - The typical base pay range for this role across the U.
S.
is USD $112,000 - $218,400 per year.
There is a different range applicable to specific work locations, within the San Francisco Bay area and New York City metropolitan area, and the base pay range for this role in those locations is USD $145,800 - $238,600 per year.
Certain roles may be eligible for benefits and other compensation.
Find additional benefits and pay information here:
https:
//careers.
microsoft.
com/us/en/us-corporate-payMicrosoft will accept applications for the role until May 16, 2024.
Microsoft is an equal opportunity employer.
All qualified applicants will receive consideration for employment without regard to age, ancestry, color, family or medical care leave, gender identity or expression, genetic information, marital status, medical condition, national origin, physical or mental disability, political affiliation, protected veteran status, race, religion, sex (including pregnancy), sexual orientation, or any other characteristic protected by applicable laws, regulations and ordinances.
We also consider qualified applicants regardless of criminal histories, consistent with legal requirements.
If you need assistance and/or a reasonable accommodation due to a disability during the application or the recruiting process, please send a request via the Accommodation request form.
Benefits/perks listed below may vary depending on the nature of your employment with Microsoft and the country where you work.
#azurehwjobs #HIFEOwnership of flows and automation for critical tools (place & route, extraction/STA, physical verification, etc); deploy and test new flows; debug issues & improve existing flows.
Work closely with Physical Design and Front End team members across functions and geographies to monitor, track, and resolve issues in tools and design flows.
Work with tool vendors to resolve key design challenges, improve our flows, and resolve tool issues.
Work closely with Physical Design team members to drive quality and QOR improvements.
Employment typeFull-TimeWork siteUp to 50% work from homeRole typeIndividual ContributorDisciplineSilicon EngineeringProfessionHardware Engineering.
Estimated Salary: $20 to $28 per hour based on qualifications.
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